The use of partially depleted/silicon-on-insulator (PD/SOI) transistors is known in the industry. FIG. 1 illustrates a cross-sectional view of a PD/SOI transistor. The elements of the transistor 100 are not shown in proportion. The transistor 100 comprises a substrate 114. Formed on the substrate are a source 102, a drain 104, and a floating body region 110 between the source 102 and drain 104. Above the source 102, drain 104, and body region 110 are a gate 106 and insulator layers 108. The insulator layers 108 can be oxide, nitride, a combination of oxide and nitride, or some other insulating material. Another insulator layer 112 resides between the floating body 110 and the rest of the substrate 114, isolating the body 110. When the transistor 100 is charged after being dormant for a significant amount of time, excess charge builds within the floating body 110 due to slow carrier recombination/generation processes. As the excess charge builds, the threshold voltage of the transistor 100 is lowered and varies over time. This variance is known in the industry as the “hysteresis” effect. Eventually, the transistor 100 reaches a steady state.
Because of the hysteresis effect, the switching speed of the PD/SOI transistor 100 varies depending on its switching history. The speed at which transistors switch is typically measured using a ring oscillator. FIG. 2A illustrates a conventional ring oscillator. The ring oscillator comprises an odd number of inverter circuits 202, 204, . . . utilizing PD/SOI transistors, with the output of the last inverter circuit coupled to the input of the first inverter circuit, forming a ring.
However, with a ring oscillator, the first and second switching speeds are not measurable, as the ring oscillator runs in steady state. To measure the first and second switching speeds, an open delay chain is typically used. FIG. 2B illustrates a conventional delay chain. The delay chain comprises a plurality of inverter circuits 202, 204, . . . utilizing PD/SOI transistors.
FIG. 2C illustrates two stages of conventional inverter circuits in either the ring oscillator or the delay chain. An inverter circuit 202 of the first stage comprises a first PD/SOI n-channel metal oxide semiconductor field effect transistor (MOSFET) 208 and a first PD/SOI p-channel MOSFET 206, coupled as shown. The inverter circuit 202 is powered with a voltage VDD. Another inverter circuit 204 of a second stage comprises a second n-channel PD/SOI MOSFET 212 and a second p-channel PD/SOI MOSFET 210.
In FIG. 2C, assume that the voltage of Node A has been held low (0V) for a long time, and then starts transitioning between high (VDD) and low (0V) rapidly. In the steady state, with Node A low, transistor 208 is turned off, transistor 206 is turned on, and Node B is high (VDD). As Node A transitions to VDD, transistor 208 turns on, 206 turns off, and Node B goes to 0V. This first delay between the transitions of Node A and Node B is called first switch.
Later, as Node A returns to 0V, transistors 208 and 206 revert to being off and on, respectively. When Node A goes to VDD again, transistor 208 and 206 switch on and off again, respectively, and Node B goes to 0V. This second delay between the transitions of Node A and B is called second switch. Although the external nodes of the transistors switch through exactly the same voltages, first switch and second switch delays in PD/SOI transistors are different. This is because the first switch has altered the voltage of the floating bodies of transistors 206 and 208, changing their threshold voltages, and causing the delay of the second switch to be different.
Eventually, a steady state is reached. Due to the hysteresis effect, the first switch, second switch, and steady state all have different speeds, and the difference in these speeds is a key metric for SOI technology. The speeds of the first and second switches approximately bracket the range of delay that will occur between the initial waveform propagation and steady state.
However, in order to accurately measure the difference between the first and second switching speeds, the delay chain usually requires thousands of stages. This utilizes a lot of area on a silicon wafer, making the measuring process costly.
Accordingly, there exists a need for a method and apparatus for reducing a number of stages for measuring first and second switching speeds for PD/SOI transistors. The present invention addresses such a need.